For this project, my task was to design and test a UART. I designed the UART in Verilog and linked it up to a soft-core processor to be ran on an FPGA.
As you can see from the top level diagram on the left, the basic UART settings could be set via the switches of the FPGA. I also implemented a simple call and response interrupt system for the UART to notify the CPU of incoming information.
The UART design itself is comprised of the Rx (read) and Tx (transmit) blocks as well as some simple case logic to deal with variable baud rates and other settings.
Once the UART was successfully reading, transmitting, and decoding serial data, I then moved onto interfacing with the CPU.
The main job of the processor for my case would be to run some simple code which allowed me to test my UART outside of simulation, and instead with a terminal display.
I wrote some Assembly code and initialized the TramelBlaze processor's memory with it so that on start up, it would begin a simple terminal based program.
The program would display a simple welcome text. It would print incoming ACII characters received from a keyboard input. It also dealt with [enter] to make a new line, and [backspace] to remove characters. It would also display my hometown's name upon receiving an * character, and it would write the current character count upon receiving an @ character.