440 Design Review.pptxWith a partner, I designed a Harvard architecture MIPS based processor and tested it with simulation runs through Verilog test-benches.
We successfully created a working design with 4 instruction types, IO and Memory peripherals, and added some additional instructions.
We also attempted to rework the original design to work with pipelining to increase overall instruction speed, however we ran out of time for the project before working out all of the issues associated with the retroactive design changes.
We meticulously documented the project workings in our ISA.
Harvard Memory Design
With 4 Instruction Formats
Register, Immediate, and Jump types
Plus a special format for extra instructions
One of the core parts of the design is of course the Control Unity called (MCU) for us.
We implemented control design on a simple 3 state State Machine with a case statement dependent on the Instruction Register Data on the incoming instruction.
The state Machine first, Fetches, Decodes, then Executes each incoming instruction. An Example instruction written in Verilog shown below.
Our design outputs results to the console window and shows updates in registers.
To test our working design, we loaded the memory with example Assembly Code to check for expected changes in register values. Example Code shown below.
to see the full ISA with all of our source code and full explanations.